1. Field of the Invention
The present invention relates to a thin film magnetic memory device, and more particularly to a random access memory including memory cells having magnetic tunnel junctions (MTJs).
2. Description of the Background Art
As a memory capable of storing nonvolatile data with low power consumption, attention is being paid to an MRAM Magnetic Random Access Memory) device. The MRAM device is a memory which stores nonvolatile data using a plurality of thin film magnetic materials formed on a semiconductor integrated circuit and which can randomly access the respective thin film magnetic materials.
Recently, in particular, it has been made public that the performance of an MRAM device dramatically advances by employing tunnel magneto-resistive elements which are thin film magnetic materials using magnetic tunnel junctions in memory cells. The MRAM device which includes memory cells each having a magnetic tunnel junction is disclosed by technical documents such as xe2x80x9cA 10 ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cellxe2x80x9d, ISSCC Digest of Technical Papers, TA7.2, Feb. 2000., xe2x80x9cNonvolatile RAM based on Magnetic Tunnel Junction Elementsxe2x80x9d, ISSCC Digest of Technical papers, TA7.3, Feb. 2000., and xe2x80x9cA 256 kb 3.0V 1T1MTJ Nonvolatile Magnetoresistive RAMxe2x80x9d, ISSCC Digest of Technical Papers, TA7.6, Feb. 2001.
FIG. 30 is a schematic diagram showing the configuration of a memory cell having a magnetic tunnel junction (which will be also referred to simply as xe2x80x9cMTJ memory cellxe2x80x9d hereinafter).
Referring to FIG. 31, each MTJ memory cell includes a tunnel magneto-resistive element TMR the electric resistance of which changes according to stored data level, and an access element ATR for forming the path of a sense current Is which passes through tunnel magneto-resistive element TMR during data read. In the following description, access element ATR will be also referred to as xe2x80x9caccess transistor ATRxe2x80x9d. Access transistor ATR is connected in series to tunnel magneto-resistive element TMR.
For each MTJ memory cell, a digit line DL for instructing data write, a word line WL for executing data read and a bit line BL which is a data line for transmitting an electrical signal corresponding to the data level of stored data during the data read and data write are arranged.
FIG. 31 is a conceptual view for describing a data read operation for reading data from a MTJ memory cell.
Referring to FIG. 30, tunnel magneto-resistive element TMR includes a ferromagnetic material layer FL which has a fixed, constant magnetization direction (which will be also referred to simply as xe2x80x9cfixed magnetic layerxe2x80x9d hereinafter) and a ferromagnetic material VL magnetized in a direction according to a magnetic field applied from externally (which will be also referred to simply as xe2x80x9cfree magnetization layerxe2x80x9d hereinafter). A tunnel barrier (tunnel film) TB formed out of an insulating film is provided between fixed magnetization layer FL and free magnetization layer VL. Free magnetization layer VL is magnetized in the same direction or the opposite direction to that of fixed magnetization layer FL in accordance with the level of stored data to be written. Fixed magnetization layer FL, tunnel barrier TB and free magnetization layer VL form a magnetic tunnel junction.
During data read, access transistor ATR is turned on in response to the activation of word line WL and tunnel magneto-resistive element TMR is connected between bit line BL and a ground voltage GND. As a result, a bias voltage in accordance with a bit line voltage is applied to the both ends of tunnel magneto-resistive element TMR and a tunnel current flows in tunnel film (tunnel barrier) TB. By using such a tunnel current, it is possible to carry a sense current to the current path of bit line BLxe2x80x94tunnel magneto-resistive element TMRxe2x80x94access transistor ATRxe2x80x94ground voltage GND.
The electrical resistance of tunnel magneto-resistive element TMR changes according to the relative relationship between the magnetization direction of fixed magnetization layer FL and that of free magnetization layer VL. Specifically, if the magnetization direction of fixed magnetization layer FL is parallel to that of free magnetization layer VL, the electrical resistance value of tunnel magneto-resistive element TMR is a minimum value Rmin. If these magnetization directions are opposite (non-parallel) to each other, the electrical resistance value of tunnel magneto-resistive element TMR is a maximum value Rmax.
Accordingly, if free magnetization layer VL is magnetized in a direction according to stored data, a voltage change which occurs to tunnel magneto-resistive element TMR due to sense current differs according to the level of the stored data. Therefore, if sense current Is is carried to tunnel magneto-resistive element TMR after precharging bit line BL with, for example, a constant voltage, the stored data of the MTJ memory cell can be read by sensing the voltage of bit line BL.
FIG. 32 is a conceptual view for describing a data write operation for writing data to the MTJ memory cell.
Referring to FIG. 32, during data write, word line WL is deactivated and access transistor ATR is turned off. In this state, a data write current for magnetizing free magnetization layer VL in a direction according to the write data, is carried to each of digit line DL and bit line BL.
FIG. 33 is a conceptual view for describing the relationship between the data write current and the magnetization direction of tunnel magneto-resistive element TMR during data write.
Referring to FIG. 33, the horizontal axis H(EA) indicates a magnetic field applied in an easy axis (EA: Easy Axis) direction in free magnetization layer VL in tunnel magneto-resistive element TMR. The vertical axis H(HA) indicates a magnetic field applied in a hard axis (HA: Hard Axis) direction in free magnetization layer VL. Magnetic fields H(EA) and H(HA) correspond to two magnetic fields generated by currents carried to bit line BL and digit line DL, respectively.
In the MTJ memory cell, the fixed magnetization direction of fixed magnetization layer FL is along the easy axis of free magnetization layer VL. Free magnetization layer VL is magnetized in a direction parallel or non-parallel (opposite) to fixed magnetization layer FL along the easy axis direction in accordance with the level of stored data (xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d). The MTJ memory cell can store 1-bit data (xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d) corresponding to the two magnetization directions of free magnetization layer VL, respectively.
The magnetization direction of free magnetization layer VL can be rewritten only if the sum of magnetic fields H(EA) and H(HA) applied to free magnetization layer VL reaches a region outside of an asteroid characteristic line shown in FIG. 33. In other words, if the data write magnetic field applied to free magnetization layer VL has an intensity corresponding to the region inside of the asteroid characteristic line, the magnetization direction of free magnetization layer VL has no change.
As shown in the asteroid characteristic line, if a magnetic field in the hard axis direction is applied to free magnetization layer VL, it is possible to decrease a magnetization threshold necessary to change the magnetization direction of free magnetization layer VL along the easy axis.
If operation points during data write are designed as shown in the example of FIG. 33, the data write magnetic field in the easy axis direction is designed so as to have an intensity of HWR in the MTJ memory cell to which the data is to be written. That is, the value of the data write current carried to each of bit line BL and digit line DL is designed so as to obtain this data write magnetic field HWR. Generally, data write magnetic field HWR is expressed by the sum of a switching magnetic field HSW necessary to change over a magnetization direction and a margin xcex94H, i.e., HWR=HSR+xcex94H.
To rewrite the stored data of the MTJ memory cell, i.e., to rewrite the magnetization direction of tunnel magneto-resistive element TMR, it is necessary to carry a data write current at predetermined level or higher to each of digit line DL and bit line BL. By doing so, free magnetization layer VL in tunnel magneto-resistive element TMR is magnetized in the direction parallel or opposite (non-parallel) to that of fixed magnetization layer FL in accordance with the direction of the data write magnetic field along the easy axis (EA). The magnetization direction which is written to tunnel magneto-resistive element TMR once, i.e., the stored data of the MTJ memory cell is held in a nonvolatile manner until new data is written.
As described above, the electrical resistance of tunnel magneto-resistive element TMR changes according to the magnetization direction which can be rewritten by the data write magnetic field applied thereto. Therefore, if electrical resistance values Rmax and Rmin of tunnel magneto-resistive element TMR are made to correspond to the levels (xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d) of the stored data, respectively, it is possible to store nonvolatile data.
FIG. 34 is a block diagram showing the configuration of a column select related circuit and a column select target memory array in an MRAM device in which MTJ memory cells are integrated and arranged in a matrix.
Referring to FIG. 34, memory array MA includes memory cells arranged in a matrix. The column select related circuit includes bit lines BL less than 0 greater than  to BL less than n greater than  (to be also referred to generically as xe2x80x9cbit lines BLxe2x80x9d hereinafter) arranged to correspond to memory cell columns included in memory array MA, respectively, write current control circuits BLCLa and BLCLb which are arranged on the both sides of memory array MA and supply data write currents to bit lines BL, respectively, current sources 600 which supply currents to write current control circuits BLCLa and BLCLb, respectively, column decoders 200a and 200b which execute column selection and transmit column selection results to column select lines CSL and CSLR, respectively.
Write current control circuit BLCLa includes a plurality of write control units BLUa provided to correspond to one end sides of bit lines BL less than 0 greater than  to BL less than n greater than , respectively. Write current control circuit BLCLb includes a plurality of write control units BLUb provided to correspond to the other end sides of bit lines BL less than 0 greater than  to BL less than n greater than , respectively. It is assumed herein that the one end side signifies a write current control circuit BLCLa side and the other end side signifies a write current control circuit BLCLb side. If write enable WE is active (at xe2x80x9cHxe2x80x9d level), column decoder 200a transmits a column select result to column select lines CSL less than 0 greater than  to CSL less than n greater than  (to be also referred to generically as xe2x80x9ccolumn select lines CSLxe2x80x9d hereinafter) which correspond to the plurality of write control units BLUa included in write current control circuit BLCLa, respectively, in accordance with the inputs of column addresses CA less than y:0 greater than  (where y is a natural number). In addition, if write enable WE is active (at xe2x80x9cHxe2x80x9d level), column decoder 200b transmits a column select result to column select lines CSLR less than 0 greater than  to CSLR less than n greater than  (to be also referred to generically as xe2x80x9ccolumn select lines CSLRxe2x80x9d hereinafter) which correspond to the plurality of write control units BLUb included in write current control circuit BLCLb, respectively, in accordance with the inputs of column addresses CA less than y:0 greater than  (where y is a natural number). It is noted that column addresses CA less than y:0 greater than  generically express column addresses CA less than 0 greater than  to CA less than y greater than  of a plurality of bits. The other signals each consisting of a plurality of bits will be also expressed similarly so as to generically show the plural bits. For example, ith to jth bits of a signal SIJ will be also expressed generically by signals SIJ less than i:j greater than . Column addresses CA less than y:0 greater than  will be also referred to generically as xe2x80x9ccolumn addresses CAxe2x80x9d hereinafter.
FIG. 35 is a circuit diagram showing the configuration of write control unit BLUa in detail.
Referring to FIG. 35, write control unit BLUa includes a NAND circuit 52 which outputs a NAND logic operation result for write data NWDT (an inverted signal of write data WDT) and the voltage level of column select line CSL which shows a column select result, and a P-channel MOS transistor 50 and an N-channel MOS transistor 51 which are complementarily activated in accordance with the output signal of NAND circuit 52.
In addition, write control unit BLUb has the same configuration as that of write control unit BLUa except that signal NWDT inputted into NAND circuit 52 is replaced by write data WDT as indicated in a bracket.
The operations of write control units BLUa and BLUb will be described.
Write control unit BLUa arranged on the one end side of bit line BL connects the one end side of bit line BL to a power supply voltage VCC in accordance with the activation of P-channel MOS transistor 50. Write control unit BLUb arranged on the other end side of bit line BL connects the other end side of bit line BL to ground voltage GND in accordance with the activation of N-channel MOS transistor 51. Following this, a data write current i0 is supplied from the one end side of bit line BL to the other end side thereof. On the other hand, write control unit BLUa arranged on the one end side of bit line BL connects one end side of bit line BL to ground voltage GND in accordance with activation of N-channel MOS transistor 51. Write control unit BLUb arranged on the other end side of bit line BL connects the other end side of bit line BL to power supply voltage VCC in accordance with activation of P-channel MOS transistor 50. Accordingly, a data write current i1 is supplied from the other end side of bit line BL to the one end side thereof.
Referring back to FIG. 34, it is assumed herein that data write current i0 is carried to bit line BL in a direction from write current control circuit BLCLa toward write current control circuit BLCLb. It is also assumed herein that data write current i1 is carried to bit line BL in a direction from write current control circuit BLCLb toward write current control circuit BLCLa.
FIG. 36 is a signal waveform view showing the waveforms of respective signal lines if bit line BL less than 0 greater than  is selected. Now, a case where data write current i0 is supplied to bit line BL less than 0 greater than  will be described.
At time tA at which the level of write data WDT becomes xe2x80x9cHxe2x80x9d level, write data WDT (at xe2x80x9cHxe2x80x9d level) is inputted into write current control circuit BLCLb. In addition, write data NWDT (at xe2x80x9cLxe2x80x9d level) which is the inverted signal of write data WDT is inputted into write current control circuit BLCLa through an inverter 30.
At time tB, write enable WE is activated (to xe2x80x9cHxe2x80x9d level), and column decoder 200a which is provided to correspond to write current control circuit BLCLa selectively activates column select line CSL less than 0 greater than  (sets column select line CSL less than 0 greater than  at xe2x80x9cHxe2x80x9d level) among column select lines CSL less than 0 greater than  to CSL less than n greater than  in accordance with the inputs of write enable WE and column address CA. Column decoder 200b which is provided to correspond to the other write current control circuit BLCLb selectively activates column select line CSLR less than 0 greater than  (sets column select line CSLR less than 0 greater than  at xe2x80x9cHxe2x80x9d level) among column select lines CSLR less than 0 greater than  to CSLR less than n greater than  in accordance with the inputs of write enable WE and column address CA.
Following this, two write control units BLUa and BLUb, which are arranged on the both sides of bit line BL less than 0 greater than  corresponding to column select lines CSL less than 0 greater than  and CSLR less than 0 greater than , are activated, respectively. Write control unit BLUa corresponding to column select line CSL less than 0 greater than  connects one end side of selected bit line BL less than 0 greater than  to ground voltage GND. Write control unit BLUb corresponding to column select line CSLR less than 0 greater than  connects the other end side of selected bit line BL less than 0 greater than  to power supply voltage VCC. Therefore, data write current i1 is carried to selected bit line BL less than 0 greater than  in a direction from the other end side of bit line BL less than 0 greater than  toward the one end side thereof. In this way, it is possible to supply data write current i0 or i1 in the direction according to the level of write data WDT to a selected bit line as a select target.
With this configuration, however, it is necessary to provide write control units BLU each of which performs decoding in accordance with the operation result for the column select result and the data signal on the both sides of the memory array for each bit line, which disadvantageously increases the area of the circuit zone of the write current control circuit.
This disadvantage becomes conspicuous particularly for a mass storage memory array.
The reason is as follows. The highest current value which can be carried to the digit line and the bit line during data write is restricted by a wiring resistance and a power supply voltage. Therefore, if the number of memory cells connected to one bit line BL increases, the wiring resistance of the bit line increases. To avoid increasing the wiring resistance according to an increase in the length of the bit line, it is necessary to divide the memory array into a plurality of memory blocks and to divide and hierarchize the bit line. This is because it is necessary provide the write current control circuits of the same configuration as that shown in FIG. 34 on the both sides of each memory block for each memory block. As a result, the area of the circuit zone of the write related current increases. Further, during data read, it is necessary to provide a gate transistor for selecting a bit line for each bit line, which disadvantageously increases the area of the circuit zone of the read related circuit.
It is an object of the present invention to provide a thin film magnetic memory device capable of reducing areas of write system and read system circuits, and also reducing the overall circuit area even in a mass storage MRAM device.
According to one aspect of the present invention, there is provided a thin film magnetic memory device which includes: first to Nth N memory blocks, where N is a natural number not smaller than 2; a plurality of bit lines; and first to (N+1)th (N+1) write control circuits. Each of the N memory blocks has a plurality of memory cells, each storing magnetically written data, arranged in a matrix, and shares columns of a plurality of memory cells. The plurality of bit lines are provided to correspond to the plurality of memory cell columns, respectively, and shared among the N memory blocks. The (N+1) write control circuits are each arranged alternately with each of the memory blocks using regions adjacent in a row direction to each of the memory blocks. Each of the (N+1) write control circuits is connected to the plurality of bit lines, and supplies a data write current to a selected bit line of the plurality of bit lines during the data write in accordance with a level of write data. If the Ith memory block of the N memory blocks, where I is a natural number from 1 to N, is selected, each of first to Ith write control circuits electrically connects the selected bit line to one of first and second voltages according to the write data and each of (I+1)th to (N+1)th write control circuits electrically connects the selected bit line among the plurality of bit lines to the other one of the first and second voltages according to the write data.
Therefore, the advantage of the thin film magnetic memory device of the present invention is in that with the constitution in which the memory has a mass storage capacity and divided memory blocks, it is possible to reduce the area of the overall write control circuits.
According to another aspect of the present invention, there is provided a thin film magnetic memory device which includes: first to Nth N memory blocks where N is a natural number not smaller than 2; first to (N+1)th (N+1) write control circuits; first and second data lines; and first and second address decoders. Each of the N memory blocks has a plurality of memory cells, each storing magnetically written data, arranged in a matrix, and shares memory cell columns among them. Each of the memory blocks includes a plurality of bit lines provided to correspond to a plurality of memory cell columns, respectively. The (N+1) write control circuits are each arranged alternately in a column direction with each of the N memory blocks for each of the memory blocks, and each supplies a data write current to a selected bit line of the plurality of bit lines in accordance with a level of write data during data write. The first data line is arranged to be common to the odd-numbered write control circuits of the (N+1) write control circuit. The second data line is arranged to be common to the even-numbered write control circuits of the (N+1) write control circuit. The first address decoder transmits first and second data signals, complementary to each other in accordance with the write data, to the first and second data lines, respectively. Two of the write control circuits adjacent a selected memory block among the N memory blocks are selected during the data write. Each of the write control circuits includes: at least one of first and second connection control circuits and a driver. The first connection control circuit controls the connection between one end sides of the plurality of bit lines and a shared node provided for each of the write control circuits. The second connection control circuit controls the connection between the other end sides of the plurality of bit lines and the shared node in each of the memory blocks. The driver is connected to one of the first and second data lines and electrically connects the shared node to one of the first and second voltages in accordance with the one of the first and second data signals during the data write. The plurality of second address decoders are provided to correspond to the plurality of write control circuits, respectively, and each controls one of the first and second connection control circuits in accordance with a memory block select signal for selecting the selected memory block and a column select result.
According to the thin film magnetic memory device of the present invention, it is possible to share the write control circuit arranged between the two memory blocks among the two memory blocks.
Therefore, the advantage of the thin film magnetic memory device of the present invention is in that with the constitution in which the memory has a mass storage capacity and divided memory blocks, it is possible to reduce the respective write control circuits arranged alternately with the respective memory blocks as a whole and to reduce the area of the circuit zone of each write control circuit.
According to yet another aspect of the present invention, there is provided a thin film magnetic memory device which includes: a memory array; a plurality of data line pairs; a plurality of driver units; first and second connection control circuits; and an address decoder. The memory array has a plurality of memory cells, each storing magnetically written data, arranged in a matrix. The memory array includes a plurality of bit lines provided to correspond to a plurality of memory cell columns, respectively. The memory array is divided along a row direction into a plurality of block units, respectively. The plurality of data line pairs are provided to correspond to the plurality of block units, respectively. The plurality of driver units are provided to correspond to the plurality of data line pairs, respectively, and each selectively supplies a data write current to corresponding one of the data line pairs in accordance with a column select result during data write. The first connection control circuit is provided for each of the data line pairs. The second connection control circuit is provided for each of the data line pairs. Each of the data line pairs includes first and second data lines. The first connection control circuit includes a plurality of first switch circuits each controlling the connection between one end side of each bit line of the bit lines included in the corresponding block unit and the corresponding first data line. The second connection control circuit includes a plurality of second switch circuits each controlling the connection between the other end side of each of the bit lines included in the corresponding block unit and the corresponding second data line. The address decoder selectively turns on the plurality of first and second switch circuits in accordance with the column select result.
According to the thin film magnetic memory device of the present invention, the memory array is divided into a plurality of block units and connection control circuits are provided to correspond to the respective block units. Each connection control circuit controls the connection between the corresponding data line pair and each bit line included in each block unit. That is, each connection control circuit is provided with switch circuits turned on/off in accordance with the column select result to correspond to one end side and the other end side of each bit line BL, respectively. Accordingly, it is possible to supply a data write current to the selected bit line.
Therefore, the advantage of the thin film magnetic memory device of the present invention is in that since the data write operation can be executed under the control of the transistors included in each connection control circuit with the constitution of hierarchical bit lines, it is possible to greatly decrease the number of parts of each write control circuit and to reduce the area of the write control circuit.